The present invention pertains to the field of programmable logic device architectures, and more particularly to a logic block and programmable interconnect network specially adapted for use as an optimized emulation and prototyping logic chip.
General purpose programmable logic chips that are available as off-the-shelf components (i.e., are commercially available) are generally not custom designed for special applications such as logic emulation, prototyping and computing. Examples of a general purpose programmable logic chips are field programmable gate arrays (xe2x80x9cFPGAsxe2x80x9d), programmable logic arrays (xe2x80x9cPLAsxe2x80x9d), and programmable array logic (xe2x80x9cPALsxe2x80x9d). General-purpose programmable logic chips have served adequately in the initial development of applications such as hardware logic emulation, prototyping and computing. However, in these applications, general-purpose logic chips have some drawbacks. Many general-purpose logic chips emphasize speed and density (i.e., how many logic gates can be implemented in a single chip) above other goals. To be cost effective for most applications, a general-purpose programmable logic architecture should provide routing resources sufficient to give a good chance of fitting a design therein and allowing the use of most of the available logic gates in the integrated circuit. However, with a general-purpose programmable logic architecture, there is always a possibility that a given design or partition may not be implementable, even though the gate count (i.e., the number of gates that the manufacturer of the programmable logic chip claims the chip can implement) is within the rated capacity of the chip. Also, the speed of the compile process is of lesser importance in the general purpose logic chip.
In contrast, in a logic emulation, prototyping or computing application, the priorities are different. The logic chip is normally part of a larger, multi-chip system, often with tens or hundreds of logic chips. Large input design netlists must be automatically compiled into all these logic chips with a very high degree of success and a minimum of user intervention. A netlist is a description of a logic design that specifies the components of the design (e.g., the logic gates) and how the components are interconnected. Each xe2x80x9cnetxe2x80x9d of a netlist defines a circuit path between pins on a component or an input/output pad. It is essential that the logic chip used in these applications provide routing resources which are flexible and capable enough to nearly always succeed in allowing most of the logic resources to be used by a fully automatic compile process. This compile process should execute rapidly. Fast compile times minimize the time required to get from the time the user""s design is presented to the emulator system to the time all the logic chips are programmed and ready to run the user""s design (i.e., emulate the user""s design).
The differences between the goals of the general purpose logic chip and the goals of a logic chip used in emulation, prototyping and computing applications present a situation where there is a need for a logic chip which is specialized for logic emulation, prototyping and computing applications.
The present invention is directed to a programmable logic device architecture that is particularly useful in logic emulation, prototyping and/or computing applications. A particular embodiment of the present invention comprises a plurality of logic elements, which is divided into a plurality of subsets of logic elements. In a preferred embodiment of the present invention, each of the plurality of logic elements comprises data selector logic.
The logic chip further comprises a plurality of first level interconnects. The plurality of first level interconnects interconnect one of the plurality of subsets of logic elements, thereby forming a plurality of first level logical units. The plurality of first level logical units is divided into a plurality of subsets of first level logical units. The logic chip also comprises a plurality of second level interconnects. In a preferred embodiment, the plurality of second level interconnects comprises a partial crossbar interconnect. The second level interconnects interconnect one of the plurality of subsets of first level logic units, thereby forming a plurality of second level logic units. The logic chip also comprises a third level interconnect. In a preferred embodiment, the third level interconnect comprises a partial crossbar interconnect. The third level interconnect interconnects the plurality of second level logic units, thereby forming a third level logic unit.
In a particular aspect of the present invention, the plurality of first level interconnects comprise a plurality of fully and partially populated crossbars. A particular embodiment of a partially populated crossbar can comprise a plurality of groups of inputs and a plurality of multiplexers. Each of the plurality of multiplexers comprises at least two data inputs, at least one select input and at least one output. Each input of the plurality of groups of inputs electrically communicates with the data inputs of one of the plurality of multiplexers. At least one select input on each of the plurality of multiplexers is electrically connected to a decoder, which is electrically connected to a programming cell. A programmable crosspoint is in electrical communication between the output of each of the plurality of multiplexers and the crossbar output pin. The programmable crosspoint comprises a pass transistor and a programmable memory cell.
The partial crossbar architecture used in the preferred second and third level interconnects is powerful, flexible and reduces the amount of time it takes to compile a user""s design into a system-level logic emulation application.
Implementations of partial crossbar interconnects on a chip may take different forms than they do at the system level, since the logic blocks being interconnected, the crossbars and the interconnecting wires are all in the same medium, not separated into different packages. This invention includes several ways of implementing partial crossbar interconnections on a chip. The partial crossbar interconnect may be applied hierarchically, using multiple levels of crossbars to span large numbers of logic blocks more efficiently than a single-level partial crossbar interconnect.
The above and other preferred features of the invention, including various novel details of implementation and combination of elements will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular methods and circuits embodying the invention are shown by way of illustration only and not as limitations of the invention. As will be understood by those skilled in the art, the principles and features of this invention may be employed in various and numerous embodiments without departing from the scope of the invention.